In recent years, semiconductor LSIs, chip parts, etc. have been being miniaturized with narrower terminal pitches, and multilayer ceramic substrates, on which they are mounted, are required to have narrower pitches with higher dimensional precision. Multilayer ceramic substrates widely used at present are insulating, sintered alumina substrates, on which wirings of high-melting-point metals such as tungsten, molybdenum, etc. are formed. However, because high-melting-point metals such as tungsten, molybdenum, etc. have large electric resistance, and large high-frequency loss, they cannot be used in parts needing low-resistance wiring and high-frequency parts. Thus, low-temperature-sinterable multilayer ceramic substrates, on which low-resistance metals such as copper, silver, gold, etc. are used in place of metals such as tungsten, molybdenum, etc., have been finding applications particularly in parts for cell phones. When low-melting-point metals such as copper, silver, gold, etc. are used, multilayer ceramic substrates should be densely sintered at as low temperatures as about 800-1000° C. The low-temperature-sinterable multilayer ceramic substrates are those made of low-temperature-co-firable ceramics (LTCC), which are called “LTCC substrates.”
In a sintering step for forming multilayer ceramic substrates, the ceramics shrink about 10-20%. Because of variations in quality among inorganic material powder lots, in composition among binders for green sheets and in particle size among powders constituting green sheets, etc., it is extremely difficult to keep a constant shrinkage ratio. Shrinkage ratios may vary nearly ±1% among lots. Also, because internal circuit patterns or surface conductor patterns formed by pastes of low-melting-point metal powder such as silver are different from ceramics in sintering shrinkage, the sintered LTCC substrates suffer deformation such as warp. To reduce such shrinkage ratio variations and deformation, circuit patterns inside or on the surface should be selected depending on green sheet lots, or a ceramic paste applied to the top and bottom surfaces of the laminate should have different shrinkage ratios.
To solve such problems, Japanese Patent 2554415 discloses a method comprising bringing a flexible constraint layer comprising non-metal inorganic particles dispersed in an organic binder into contact with a surface of a ceramic green body formed by a mixture comprising ceramic powder dispersed in an organic binder and a sinterable inorganic binder (glass component), evaporating the organic binder from both of the ceramic green body and the constraint layer, sintering them, and removing the constraint layer from the sintered ceramic body. In this method, the sinterable inorganic binder contained in the ceramic green body penetrate into the constraint layer as deep as 50 μm or less to bond the ceramic green body to the constraint layer, but the constraint layer of inorganic particles is not substantially sintered, so that it does not shrink, thereby suppressing the shrinkage of the ceramic green body attached to the constraint layer in a lamination plane (X-Y plane). Thus, the sintering method with suppressed shrinkage in an X-Y plane is called “shrinkage-constraining method.”
Recent trends of miniaturizing and thinning multilayer ceramic substrates, increasing the number of elements, and making circuit structures more complicated have made internal conductor patterns and via-conductors finer. Most via-conductors now have via-hole diameters of 150 μm or less after sintering, but smaller via-conductors of 100 μm and 80 μm in diameter will be needed in the future. Because fine via-holes formed by a laser are tapered, their bottoms have even smaller diameters. The reduction of via-hole diameters turns their aspect ratios (length/diameter) larger. Thus, conventional conductive pastes do not have enough fillability (chargeability), leaving large space after sintering. Such space lowers reliability in the connection between upper and lower electrodes, provides high resistance to via-conductors, and causes impregnation with a plating solution in some cases.
Because green sheets shrink about 10-20% in a usual free-sintering method, via-holes and printing patterns before sintering have large sizes taking shrinking margins into consideration. However, because no shrinkage occurs in an X-Y direction in the shrinkage-constraining method, via-holes and printing patterns before sintering should be smaller than in the free-sintering method. The shrinkage-constraining method thus needs smaller via-holes and via pads at the time of printing. Also, the thickness reduction of about 30-50% occurs in the shrinkage-constraining method because of no shrinkage in an X-Y direction, green sheets should be thicker to achieve the targeted thickness after sintering. Accordingly, via-holes to be printed should have larger aspect ratios in the shrinkage-constraining method than in the free-sintering method, resulting in more difficult filling of a conductor into the via-holes.
JP 2000-285731 A discloses a method for producing a multilayer ceramic substrate by sintering laminated green sheets and heat-shrinkage-constraining sheets attached to both surfaces thereof, in which a glass-frit-free, conductive paste comprising conductor powder, 95% by weight or more of which is Ag powder having an average particle size of 3-10 μm, and an organic vehicle, is filled into via-holes formed in the green sheets. Because sintering does not generate large deviation between the conductive paste and the green sheets in this method, gaps are unlikely provided between via-conductors and the substrate, with cracking also unlikely in the substrate. However, via-holes with smaller diameters and larger aspect ratios lower the fillability of a conductive paste into the via-holes, failing to achieve sufficient performance.
JP 1-107591 A discloses the production of an electric circuit board with improved solderability by applying a conductor composition comprising silver powder and rhodium powder and/or an organic rhodium compound dispersed in a vehicle, without substantially containing glass frit as an inorganic binder, to a substrate of glass or a low-temperature-sinterable ceramic, and sintering it. However, this reference is silent about the diameters of via-holes, and the fillability of the conductor composition into the via-holes. It is considered that the fillability of the conductor composition into the via-holes would be remarkably reduced, if the via-holes had smaller diameters and larger aspect ratios.
JP 8-274470 A discloses a multilayer circuit board obtained by laminating pluralities of layers provided with conductor patterns, comprising via-holes formed between conductor patterns on each layer, and via-conductors filled into the via-holes for connecting the conductor patterns, the outer surfaces of via-conductors containing pluralities of voids of about 1-5 μm in diameter being closely attached to the inner walls of via-holes. However, because the formation of voids needs a large amount of inorganic materials, the via-conductors have high resistance.
JP 2002-198660 A discloses a method for producing a multilayer circuit board comprising forming pluralities of thermal via-holes in each green sheet with a conductive paste comprising Ag powder having an average particle size of 5 μm or more and Ag powder having an average particle size of 1 μm or less, so that heat can be efficiently dissipated from semiconductor parts. However, because this conductive paste does not fill the via-holes enough, sufficient connection cannot be achieved between upper and lower wiring electrodes, and the circuit board has low reliability because of the impregnation of a plating solution, etc.